(1) Technical Field
The present invention relates to the fields of Very Large Scale Integration (VLSI) circuit design, electronic devices, and microelectronic circuits. More specifically, the present invention pertains to a method and apparatus for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times.
(2) Description of Related Art
The trend in the VLSI design industry is to provide the consumer with VLSI chips and semiconductor devices that perform faster, that have smaller dimensions, and that consume less power than the prior VLSI chips and semiconductor devices in the market. One example of this trend is in the area of personal computers, where every user desires their personal computer to be faster and smaller. Unfortunately, the faster a VLSI chip performs, the more power the chip absorbs, causing it to overheat which, in turn, requires that the VLSI chips be placed farther away from one another on circuit boards, and in the particular case of a personal computer, forces the system to include bulky air cooling fans. Thus, in microelectronic applications, power absorption and the need for faster performance are the two primary issues that constrain the fabrication and design of a semiconductor device.
In order to speed up the switching time for a Heterojunction Bipolar Transistor (HBT) device, the thickness of the intrinsic base layer of the HBT device must be vertically scaled down. In contrast, the thickness of the extrinsic base layer is inversely proportional to the resistance of the contacts to the base layer in the extrinsic device. Therefore, in order to decrease the power absorbed by the HBT device, an artisan must decrease the resistance of the contacts to the base layer in the extrinsic device by vertically scaling up the thickness of the extrinsic base layer. Since state of the art VLSI design techniques cannot decouple the thickness of the extrinsic base from the thickness of the base layer in the intrinsic device, vertically scaling down the base layer to improve the speed of the HBT device increases the base resistance in the extrinsic base layer, thus increasing the power being absorbed and negating some of the benefits of the reduced device scaling. Therefore, the artisans are faced with the problem of trying to simultaneously satisfy two opposing goals, since vertical and lateral scaling of HBT devices is needed to make faster HBT devices and circuits.
In recent years, methods to obtain a thicker highly-doped p+ base layer in the extrinsic region have relied on re-growing on a partially fabricated mesa. In this technique, a mask is used to pattern the emitter mesa. Subsequently, with the highly-doped p+ base layer being the exposed layer, another layer of a p-type semiconductor is grown on top of the exposed highly-doped p+ base layer. Then the mask is removed, and the processing of the HBT is completed. However, the layers grown using this technique are of poor quality and the method does not solve the problem of the resistance of the contacts to the base layer in the extrinsic device and the extrinsic base-collector capacitance in the extrinsic device.
Moreover, there have been multiple approaches to minimize the base-collector capacitance reported in the literature. In one approach, the collector layer underneath the base contacts is etched away using a technique that selectively etches the collector layer leaving the base layer untouched, as discussed in “Laterally Etched Undercut (LEU) Technique to Reduce Base-collector Capacitance in Heterojunction Bipolar Transistors,” IEEE GaAs IC Symposium, 1995, pp. 167-170, by W. Liu et al. In another approach, known as the “transferred substrate method,” the substrate is removed from the active intrinsic device. Then the collector layer is patterned so as to remove it from the extrinsic regions of the device, and then the device is attached to a host substrate, as discussed in “Submicron scaling of HBTs,” IEEE Trans. on Electronic Devices, vol. 48, no. 11, pp. 2406-2624, by M. Rodwell et al. However, both of these techniques, while good for demonstrating the high potential of such device, are not consistent with the high yields required to make complex (>10,000 transistor) integrated circuits.
Therefore, it would be desirable to provide a method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times. Such a method would allow a VLSI designer to select the thickness of an intrinsic layer independently from a thickness of its corresponding extrinsic layer, thus allowing the resulting device to have a thick extrinsic base layer (low base resistance) and a thin intrinsic base layer (short base transit times) simultaneously. Furthermore, it is desirable that the method for fabricating HBT devices has a consistent high yield of non-defective HBT devices, which are required to make accurate, complex (>10,000 transistor) integrated circuits.
For the foregoing reasons, there is a great need for a technique that fabricates heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times.
The following references are presented for further background information:    [1] W. Liu et al, “Laterally Etched Undercut (LEU) Technique to Reduce Base-collector capacitance in Heterojunction Bipolar Transistors,” IEEE GaAs IC Symposium, 1995, pp. 167-170.    [2] M. Rodwell et al, “Submicron scaling of HBTs,” IEEE Trans. on Electronic Devices, vol. 48, no. 11, pp. 2406-2624.